1. Field of the Invention
The present invention relates generally to transferring data between a hard disk drive and a host data bus and more particularly to automated hardware for controlling space in a disk drive buffer memory used in the data transfer.
2. Description of Related Art
Personal computers, sometimes referred to as microcomputers, have gained wide spread use in recent years primarily because they are inexpensive and yet powerful enough to handle computationally-intensive user applications. The data storage and data sharing capabilities of personal computers typically include one or more hard disk drives.
A hard disk drive 115 (FIG. 1) has a rotating magnetic medium 190, i.e., a disk, that is magnetized in a certain pattern by a read/write head 191 which flies above the surface of disk 190. During a write operation, head 191 creates patterns on the magnetic coating of rotating disk 190 which represent data, while in a read operation, head 191 reads the patterns created during the write operation.
In most high capacity hard disk drives, several disks are mounted above one another on a common spindle. Each of the disks has at least one read/write head per disk surface. Data are written in concentric circular tracks on the disk surface.
Data stored on a hard disk are generally divided into files. Each file represents a unit of data which is processed by computer 105. The files are stored on rotating disk 190 in sectors. The number of sectors which are written in one revolution of the disk comprises a track. Therefore, to specify the location of any particular piece of data on the disk surface a head address, a track address, and a sector number are required. The head, track, and sector addresses are sometimes referred to as the geometric address.
The operations performed in response to a request from a computer program executing in computer 105 to read data from or to write data to disk drive 115 are well known to those skilled in the art. Typically, during this operation, an electronic circuit in disk drive 115 receives a request for a particular sector of data on one of the disks in drive 115, e.g., the electronic circuit is provided the geometric address for the sector.
The electronics in disk drive 115 include a microprocessor 110, typically a first generation microprocessor such as microprocessors Model No. 8080/8085 sold by Intel Corporation of Sunnyvale, Calif., a storage controller integrated circuit 100 that interfaces microprocessor 110, drive electronics 185, host interface bus 175, and random access buffer memory 120. Drive electronics 185 (i) convert the analog signals from read/write head 191 to digital signals for storage controller integrated circuit 100, and (ii) control the mechanical operation of disk drive 115.
Host intrface bus 175 is, for example, an ISA, EISA, microchannel or SCSI bus. The structure and operation of computers with any one of these bus structures are well known to those skilled in the art.
Storage controller integrated circuit 100 includes a microprocessor interface circuit 160, a disk controller circuit 130, buffer controller 140, and host interface circuit 170. The structure and operation of storage controller integrated circuit 100 are also well-known to those skilled in the art. For example, Cirrus Logic of Fremont, Calif. offers such an integrated circuit as Model No. SH260. Chips and Technology of San Jose, Calif. offers such an integrated circuit as Model No. 82C5059. Adaptec Corporation of Milpitas, Calif. offers Model No. AIC-9110.
The operations performed by microprocessor 110 are typically determined by program instructions, i.e., firmware, that are loaded in microprocessor 110 from a non-volatile memory when disk drive 115 is turned on. When the computer provides a read/write request to circuit 100 over the host interface bus, one of a geometric address, i.e., track, head and sector, and a logic block address, for example, is provided asynchronously to host interface circuit 170. This information is stored directly in registers in circuit 170.
Upon receipt of the read/write request and the geometric address, microprocessor 110 performs the necessary operations to initialize host interface circuit 170, disk controller circuit 130 and buffer controller circuit 140 for the requested read or write operation. The initialization signals are passed from microprocessor 110 through microprocessor interface circuit 160 to the other circuits over microprocessor control bus 166. For clarity, the control signals lines between microprocessor 110 and microprocessor interface circuit 160 as well as the control signal lines between disk controller circuit 130, buffer controller circuit 140, host interface circuit 170 and RAM 120 are not shown in FIG. 1.
After initialization for a read operation, data are passed from drive electronics 185 to disk controller circuit 130 which in turn sends the data to buffer controller circuit 140. Buffer controller circuit 140 stores the data in buffer memory 120. When one or more complete sectors of data are stored in buffer memory 120, microprocessor 110 initiates a transfer of the data from buffer memory 120 to a first-in-first-out (FIFO) memory in host interface circuit 170. When the FIFO memory is nearly full, circuit 170 transfers the data over bus 175 to host computer 105.
After initialization for a write operation, data are passed from bus 175 to host interface circuit 170 which in turn sends the data to buffer controller circuit 140. Buffer controller circuit 140 stores the data in buffer memory 120. Microprocessor 110 subsequently initiates a transfer of the data from buffer memory 120 to disk controller circuit 130 which in turn transfers the data to disk drive electronics 185.
Disk and host data transfers normally occur concurrently. Buffer controller circuit 140 multiplexes access to buffer memory 120 between disk and host data transfers on a byte-per-byte basis. Hence, buffer controller circuit 140 maintains two address pointers, a read address pointer and a write address pointer, for buffer memory 120, as well as a stop pointer.
The two address pointers access all of buffer memory 120 or the segment of buffer memory allocated for the operation in a circular fashion, i.e., whenever the pointer reaches the top address of the buffer memory or the segment of buffer memory, the pointer wraps back to the bottom address of the buffer memory or segment. If after wrapping the pointer continued to increment past the starting address for the data transfer, data would be overwritten. Consequently, the stop pointer is maintained to indicate that the buffer memory or buffer memory segment is full.
Typically, the write address pointer is an up counter that holds the address of the next byte to be written to buffer memory 120. The read address pointer is an up counter that holds the next address of the next byte to be read from buffer memory 120. During a write operation, the write address pointer is used for transfer of data from host interface circuit 170 to buffer memory 120 and the read address pointer is used for transfer of the data from buffer memory 120 to disk controller circuit 130. During a read operation, the use of the pointers is reversed.
The starting and stopping addresses for a data transfer to or from buffer memory 120 is controlled solely by microprocessor 110. For example, in a read from disk 190, microprocessor 110 sets the write address pointer and the read address point to the location in buffer memory for the transfer, i.e., microprocessor 110 initializes the appropriate counters. Microprocessor 110 also initializes the stop pointer to the value of the read address pointer minus one. As each byte of data is written to buffer memory 120, the write address pointer is incremented. Similarly as each byte is read from buffer memory, the read address pointer is incremented.
Microprocessor 110 receives a signal from disk controller circuit 130 to indicate the transfer of a block, i.e., a sector, of data to buffer memory 120. Similarly, microprocessor 110 receives a signal to indicate the transfer of a block from buffer memory 120 to host interface circuit 170. Microprocessor 110 periodically updates the stop pointer based on the number of blocks that have been read from buffer memory 120 since after the data are read, the storage location is available for new data.
Data are written to buffer memory 120 until the value of the write pointer address equals the stop pointer which indicates that if another byte is written to buffer memory 120, valid data will be over written. Thus, microprocessor 110 must continuously monitor the three pointers during the data transfer and periodically update the stop pointer. This requires considerable microprocessor firmware overhead. Unfortunately, as the disk drive capacity increases and the average seek time decreases, both microprocessor clock cycles and demands for firmware increase. Therefore, buffer pointer management by microprocessor 110 limits the capability that can be supported because it requires considerable firmware as well as clock cycles to perform the operations necessary to monitor the status of buffer memory 120.